This application is related to Japanese application No. 2000-109603 filed on Apr. 11, 2000, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a cell array, a method of operating the same and a method of manufacturing the same. In particular, it relates to a cell array of virtual grounding structure including cells of split gate (SPG) structure and being capable of high integration, a method of operating the same and a method of manufacturing the same.
2. Description of Related Art
A cell array of virtual grounding structure has been proposed with a view to reducing the size of a cell array provided by integrating nonvolatile memory cells. In the virtual grounding cell array, one bit line can be omitted, because a bit line does not need to contact an impurity diffusion layer which functions as a drain, and a source of a cell can serve as a drain of another cell adjacent to the cell. Therefore, scaling of the cells is easily performed and an area of the cells can be minimized in NOR structures, which is suited to obtain a device of large capacity.
However, in the above-mentioned virtual grounding cell array, it is known that data reading from a cell is often interfered by another cell adjacent to the cell. Accordingly, it has been difficult to achieve satisfactory reading precision and to obtain a multi-valued cell array.
Regarding this drawback, a virtual grounding cell array utilizing cells of SPG structure has been proposed. FIG. 34 shows an equivalent circuit diagram of the virtual grounding cell array. Hereinafter, description is made with respect to this figure.
In FIG. 34, a memory cell 341 is constructed of a SPG transistor 342 and a control gate 343 which are connected in serial. A plurality of memory cells of this type are arranged in matrix along a direction of X parallel to a channel direction (a word line direction: referred simply to as an X direction) and a direction of Y vertical to the channel direction (a bit line direction: referred simply to as a Y direction). Control gates of the cells arranged along the X direction are connected to a common word line (WL) denoted as WL n. Drains, sources and SPGs of the cells arranged in the Y direction have a common connection to bit lines BL1 to BL5, respectively.
However, in the thus constructed cell array, it is required to separately control voltages to be applied to the SPGs (in addition to BL and WL) of the cells arranged in the Y direction. Therefore, even if an area per cell is reduced, there has been the following drawback.
As seen in FIG. 34, the SPGs of the cells are connected in the Y direction. Further, a decorder 351 as a periphery circuit is required to SPGs 1 to 4 controlling the voltage, respectively (see FIG. 35). Reference numeral 352 in FIG. 35 denotes a voltage supply. As a result, scaling of an array area is difficult.
According to the present invention, provided is a cell array comprising nonvolatile memory cells having:
a floating gate formed on a semiconductor substrate with the intervention of a first insulating film;
a split gate formed with the intervention of a second insulating film at a predetermined distance from the floating gate;
a control gate formed at least on the floating gate with the intervention of a third insulating film; and
an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitive coupled with an edge of the floating gate on an opposite side to the split gate in an X direction in parallel with a channel direction;
wherein two or more cells are arranged in matrix along the X direction and a Y direction vertical to the X direction,
the floating gates and the split gates are alternately arranged in the X direction and the impurity diffusion layer of one cell is capacitive coupled with a split gate of another cell adjacent to said one cell in the X direction,
the control gates of the cells arranged along the X direction are commonly connected along the X direction,
the impurity diffusion layers of the cells arranged along the Y direction are commonly connected along the Y direction, and
the split gates commonly connected along the Y direction are also commonly connected along the X direction through at least one conductive layer.
The present invention also provides a method of operating the above-mentioned cell array.
According to the present invention, provided is a method of manufacturing a nonvolatile semiconductor memory comprising:
(a) forming floating gates for providing a plurality of nonvolatile memory cells on a semiconductor substrate with the intervention of a first insulating film in matrix along an X direction parallel to a channel direction and a Y direction vertical to the X direction with a predetermined distance therebetween in the X and Y directions;
(b) forming a split gate on the semiconductor substrate with the intervention of a second insulating film at least at one side of each of the floating gates in the X direction so that the split gate is commonly connected with the cells arranged in the Y direction;
(c) forming an impurity diffusion layer in a surface layer of the semiconductor substrate between a floating gate of one cell and a split gate of another cell adjacent to said one cell so that the impurity diffusion layer is capacitively coupled with the floating gate of said one cell and the split gate of said another cell and commonly connected with the cells arranged in the Y direction; and
(d) forming a control gate on each of the floating gates with the intervention of a third insulating film so that the control gate is commonly connected to the cells arranged in the X direction and simultaneously forming at least one conductive layer so that the split gates commonly connected along the Y direction are also commonly connected in the X direction.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.